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Homepage>IEC Standards>IEC 61523-1:2023 - Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
download between 0-24 hoursReleased: 2023-10-11

IEC 61523-1:2023

Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)

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Standard number:IEC 61523-1:2023
Released:2023-10-11
Edition:3
ICS:25.040.01
Pages (English):640
ISBN (English):9782832275399
DESCRIPTION

IEC 61523-1:2023

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.