IEEE 1012-2024

This Verification and Validation (V&V) standard is a process standard that addresses all system, software, and hardware life cycle processes, including the Agreement, Organizational Project-Enabling, Technical Management, and Technical Process Groups. This standard is compatible with all life cycle models (e.g., system, software, and hardware); however, not all life cycle models use all of the processes listed in this standard. V&V processes determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. This determination may include the analysis, evaluation, review, inspection, assessment, and testing of products and processes. The user of this standard invokes the V&V processes associated with the life cycle processes used by the project. A description of system life cycle processes may be found in ISO/IEC/IEEE 15288:2023(E) [B41], and a description of software life cycle processes may be found in ISO/IEC/IEEE 12207:2017(E) [B40]. This standard defines the Verification and Validation Processes that are applied to the system, software, and hardware development throughout the life cycle, including acquisition, supply, development, operations, maintenance, and retirement. This standard applies to the system, software, and hardware being acquired, developed, maintained, or reused. The term software also includes firmware and microcode (e.g., field programmable gate arrays and programmable logic devices). Each of the terms system, software, and hardware includes its associated documentation.

The purpose of this standard is to achieve the following: --Establish a common framework of the V&V processes, activities, and tasks in support of all system, software, and hardware life cycle processes. --Define the V&V tasks, required inputs, and required outputs in each life cycle process. --Identify the minimum V&V tasks corresponding to a four-level integrity schema. --Define the content of the V&V plan.

Revision Standard - Active. The Verification and Validation (V&V) processes are used to determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. V&V life cycle process requirements are specified for different integrity levels. The scope of V&V processes encompasses systems, software, and hardware, and it includes their interfaces. Systems, software, and hardware being developed, maintained, or reused [legacy, commercial off-the-shelf (COTS), non-developmental items] can be the system of interest to which this standard is applied. The term software also includes firmware and microcode, and each of the terms system, software, and hardware includes related information or documentation. V&V processes include the analysis, evaluation, review, inspection, assessment, and testing of products.