IEEE 2427-2025

This standard defines a defect coverage accounting method based on simulation models for defects observed within integrated circuits (ICs). The portion of all possible defects that are detected or “covered” by tests of analog and mixed-signal circuits depends, in practice, on many factors (detectability, defect characteristics, detection threshold margin, measurement resolution, operating point, test patterns, etc.). In defining the defect coverage report process, the standard considers most of these factors. This standard focuses on defects in analog functions. In this context, “defect” is an unintended physical change in a circuit, and an “analog function” means a function that has input, internal, or output signals with meaningful values in a defined continuous range. The function has at least one parametric performance that is sufficiently non-deterministic that its test has upper and/or lower limits (the limits can be real numbers or quantized digital equivalents). This standard considers redundancy, since most analog circuits have redundancy and defect tolerance, intentional or not. This standard does not consider combinations of variations that could result in a circuit failing to meet all of its specifications; that is the subject of Monte Carlo simulations during design for yield and multi-parameter analog defect modeling. The defects considered here are applicable to purely digital circuits too, though typically a simplified fault model (stuck-at, for instance) is utilized for digital functions. Thus, this standard assumes the topic of stuck-at fault coverage accounting is addressed for digital circuits by IEEE Std 1804™, IEEE Standard for Fault Accounting and Coverage Reporting (FACR) for Digital Modules [B16].

The primary purpose of this standard is to allow people to communicate information about defect coverage in a way that allows assessment of test and circuit quality as well as prediction of important metrics [simulation time, design for test (DfT) circuit area, test time, test escapes, etc.]. Given a circuit description and a set of tests, this standard defines how to enumerate the universe of defects, determine which defects are detected by the tests, and report the coverage results. By defining analog test coverage, this standard is useful for several other purposes. First, this standard guides efficient simulation of defects to ensure that the defect models achieve a desirable trade-off between cost-effective simulation times and accurate modeling of behavior seen in real circuits. Second, this standard facilitates estimation of test escape rates (historically measured in defective parts per million [DPPM]) to facilitate trade-offs between cost of test, time to market, and quality. Third, this standard facilitates improvements in DfT and test generation methods. Many DfT and test techniques, including built-in self-test (BIST), have been developed. Despite their cost advantages, they are not used in practice because their impact on defect coverage is questioned. This is due to the lack of a well-understood and silicon-corroborated analog defect model. This standard facilitates automation and quality improvements that enables reliable comparisons of DfT and test techniques.

New IEEE Standard - Active. A defect coverage accounting method based on simulation models for defects observed within integrated circuits (ICs) is defined in this standard. The portion of a defect universe, comprising thousands or millions of reasonably likely defects, that is detected or “covered” by tests of analog and mixed-signal circuits depends on many factors, which this standard considers, such as detectability, process variations, defect characteristics, and redundancy. The contents of a defect coverage summary are specified and dozens of commonly used terms are clearly defined to aid communication about the quality of tested ICs.