IPC-J-STD-003 - Revision B

Superseded by IPC-J-STD-003-Revision-C with Amendments 1,2

This standard prescribes test methods, defect definitions and illustrations for assessing the solderability of printed board surface conductors, attachment lands, and plated-through holes utilizing either tin/lead or lead-free solders. This standard is intended for use by both vendor and user. The objective of the solderability test methods described in this standard is to determine the ability of printed board surface conductors, attachment lands, and plated-through holes to wet easily with solder and to withstand the rigors of the printed board assembly processes. This standard describes test methods by which both the surface conductors (and attachment lands) and plated-through holes may be evaluated for solderability. Test A, Test B, Test C, Test D and Test E for tin/lead solder processes and Test A1, Test B1, Test C1, Test D1 and Test E1 for lead-free solder processes, unless otherwise agreed upon between vendor and user. Test A and Test C for tin/lead solder processes, Test A1 and Test C1 for lead-free solder processes are to be used as default solderability tests. 48 pages. Released March 2007.