PRICES include / exclude VAT
Homepage>BS Standards>35 INFORMATION TECHNOLOGY. OFFICE MACHINES>35.030 IT Security>PD ISO/IEC TS 30104:2015 Information Technology. Security Techniques. Physical Security Attacks, Mitigation Techniques and Security Requirements
Sponsored link
immediate downloadReleased: 2015-05-31
PD ISO/IEC TS 30104:2015 Information Technology. Security Techniques. Physical Security Attacks, Mitigation Techniques and Security Requirements

PD ISO/IEC TS 30104:2015

Information Technology. Security Techniques. Physical Security Attacks, Mitigation Techniques and Security Requirements

Format
Availability
Price and currency
English Secure PDF
Immediate download
317.20 USD
English Hardcopy
In stock
317.20 USD
Standard number:PD ISO/IEC TS 30104:2015
Pages:42
Released:2015-05-31
ISBN:978 0 580 88642 3
Status:Standard
DESCRIPTION

PD ISO/IEC TS 30104:2015


This standard PD ISO/IEC TS 30104:2015 Information Technology. Security Techniques. Physical Security Attacks, Mitigation Techniques and Security Requirements is classified in these ICS categories:
  • 35.030 IT Security

Physical security mechanisms are employed by cryptographic modules where the protection of the modules sensitive security parameters is desired. This Technical Specification addresses how security assurance can be stated for products where the risk of the security environment requires the support of such mechanisms. This Technical Specification addresses the following topics:

  • a survey of physical security attacks directed against different types of hardware embodiments including a description of known physical attacks, ranging from simple attacks that require minimal skill or resources, to complex attacks that require trained, technical people and considerable resources;

  • guidance on the principles, best practices and techniques for the design of tamper protection mechanisms and methods for the mitigation of those attacks; and

  • guidance on the evaluation or testing of hardware tamper protection mechanisms and references to current standards and test programs that address hardware tamper evaluation and testing.

The information in this Technical Specification is useful for product developers designing hardware security implementations, and testing or evaluation of the final product. The intent is to identify protection methods and attack methods in terms of complexity, cost and risk to the assets being protected. In this way cost effective protection can be produced across a wide range of systems and needs.