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Homepage>IEC 63011-3:2018 - Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via
download between 0-24 hoursReleased: 2018-11-28
IEC 63011-3:2018 - Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

IEC 63011-3:2018

Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via

Circuits intégrés - Circuits intégrés tridimensionnels - Partie 3: Modèle et conditions de mesure des trous de liaison à travers le silicium

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English/French - Bilingual
Standard number:IEC 63011-3:2018
Released:2018-11-28
Language:English/French - Bilingual
DESCRIPTION

IEC 63011-3:2018

IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC.
Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document.