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Homepage>IEEE Standards>35 INFORMATION TECHNOLOGY. OFFICE MACHINES>35.060 Languages used in information technology>IEEE/IEC 62530-2011 - IEEE/IEC International Standard - SystemVerilog -- Unified Hardware Design, Specification, and Verification Language
Released: 19.05.2011

IEEE/IEC 62530-2011 - IEEE/IEC International Standard - SystemVerilog -- Unified Hardware Design, Specification, and Verification Language

IEEE/IEC International Standard - SystemVerilog -- Unified Hardware Design, Specification, and Verification Language

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Standard number:IEEE/IEC 62530-2011
Released:19.05.2011
ISBN:978-0-7381-6607-0
Pages:1294
Status:Active
Language:English
DESCRIPTION

IEEE/IEC 62530-2011





Adoption Standard - Active. This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.