PRICES include / exclude VAT
Homepage>BS Standards>35 INFORMATION TECHNOLOGY. OFFICE MACHINES>35.160 Microprocessor systems>BS ISO/IEC 13213:1994 Information technology. Microprocessor systems. Control and Status Registers (CSR) Architecture for microcomputer buses
Sponsored link
immediate downloadReleased: 1995-09-15
BS ISO/IEC 13213:1994 Information technology. Microprocessor systems. Control and Status Registers (CSR) Architecture for microcomputer buses

BS ISO/IEC 13213:1994

Information technology. Microprocessor systems. Control and Status Registers (CSR) Architecture for microcomputer buses

Format
Availability
Price and currency
English Secure PDF
Immediate download
486.20 USD
You can read the standard for 1 hour. More information in the category: E-reading
Reading the standard
for 1 hour
48.62 USD
You can read the standard for 24 hours. More information in the category: E-reading
Reading the standard
for 24 hours
145.86 USD
English Hardcopy
In stock
486.20 USD
Standard number:BS ISO/IEC 13213:1994
Pages:144
Released:1995-09-15
ISBN:0 580 24379 6
Status:Standard
DESCRIPTION

BS ISO/IEC 13213:1994


This standard BS ISO/IEC 13213:1994 Information technology. Microprocessor systems. Control and Status Registers (CSR) Architecture for microcomputer buses is classified in these ICS categories:
  • 35.160 Microprocessor systems

This clause summarizes the feature sets provided by the CSR Architecture and illustrates how these features are expected to be used. The CSR Architecture supports the concept of bus bridges, which (after being properly initialized) can transparently forward transactions from one compliant bus to another. This simplifies software development and encourages the use of specialized (low-cost or high-performance) bus standards. By defining a common CSR Architecture for multiple buses, the amount of customized software necessary to support each bus standard is minimized.

To improve the amount of software transparency in such multiple-bus configurations, the scope of the CSR specification includes the following:

  1. Physical Address Space Partitions. The partitioning of the address space between node CSRs and memory is defined. Both 32-bit and 64-bit addressing options are allowed.

  2. Common Transaction Sets. A common transaction set (including error-status codes) is defined. This transaction set can be transparently passed through bridges.

  3. Core CSRs. The location and meaning of the core CSRs, which are accessed during the system initialization process, are defined. This provides a uniform software interface, independent of the physical bus location.

  4. ID-ROM. The format and meaning of the node's ROM data structures are defined. The ROM directory structure supports standard and vendor-dependent data types.

  5. Interrupts. Standard target addresses are provided for interrupts that are broadcast on the bus to all nodes, or broadcast within the node (nodecast) to multiple units. Other vendor-dependent quadlet registers may be provided for interrupts that are directed to individual units.

  6. Messages. Standard target addresses are provided for messages that can be broadcast or nodecast to multiple nodes. Other vendor-dependent registers may be provided for messages that are directed to individual units.