IEEE 2416-2025

This standard describes a parameterized and abstracted power model enabling system, software, and hardware IP-centric power analysis and optimization. It defines concepts for the development of parameterized, accurate, efficient, and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage, and temperature (PVT) independence, abstracted analog and mixed-signal “AMS” power models, power and thermal management interface, and workload and architecture parameterization. Such models are suitable for use in software development flows and hardware design flows, as well as representing both pre-silicon estimated and post-silicon measured data. This standard also defines the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models, to help guide development and usage of other related power, workload and functional modeling standards, such as UPF (IEEE Std 1801), SystemC (IEEE Std 1666), and SystemVerilog (IEEE Std 1800). Beyond defining the concepts and related standard requirements, this standard also recommends the use of other relevant design flow standards [e.g., IP-XACT (IEEE Std-1685)], with the objective of enabling more complete and usable power-aware design flows. IEEE Std 2416 power models are aimed at enabling the full-system rollup of the target systems’ total power consumption.

This standard supports the ability to develop accurate, efficient, and interoperable power models for complex designs, to be used with a variety of commercial products throughout an electronic system design, analysis, and verification flows.

Revision Standard - Active. A parameterized and abstracted power model is described in this standard to enable system-, software-, and hardware IP-centric power analysis and optimization. Concepts are defined for the development of parameterized, accurate, efficient, and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage, and temperature independence; power and thermal management interface; and workload and architecture parameterization.