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Homepage>BS Standards>31 ELECTRONICS>31.180 Printed circuits and boards>PD IEC TR 61189-5-506:2019 Test methods for electrical materials, printed boards and other interconnection structures and assemblies General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501
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immediate downloadReleased: 2019-07-18
PD IEC TR 61189-5-506:2019 Test methods for electrical materials, printed boards and other interconnection structures and assemblies General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501

PD IEC TR 61189-5-506:2019

Test methods for electrical materials, printed boards and other interconnection structures and assemblies General test methods for materials and assemblies. An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501

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Standard number:PD IEC TR 61189-5-506:2019
Pages:26
Released:2019-07-18
ISBN:978 0 539 00068 9
Status:Standard
DESCRIPTION

PD IEC TR 61189-5-506:2019


This standard PD IEC TR 61189-5-506:2019 Test methods for electrical materials, printed boards and other interconnection structures and assemblies is classified in these ICS categories:
  • 31.180 Printed circuits and boards

This Technical Report is an intercomparison supporting the development of IEC 61189-5-501 in relation to the SIR method. This document sets out to validate the introduction of a new 200-µm gap SIR pattern, and was benched marked against existing SIR gap patterns of 318 µm and 500 µm.


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